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AD9139 Output not coming properly

Question asked by Erfan on Sep 12, 2017
Latest reply on Nov 30, 2017 by jerryguo

Hi Support,

 

we are using AD9139 DAC in our design. We are using 1GHz sampling clock and Data @ 500MHz DDR to generate 125MHz. We are getting the proper frequency but the waveform is not proper and smooth which is giving very high harmonic at 875MHz (Fs-Fout). Attached waveform for your reference. Can you let us know what could be the problem.

 

DAC Startup settings done:

 

## -----------------------------------------------------------------------------
## Proc name: dac_conf
## Description: DAC Start up sequence routine
## -----------------------------------------------------------------------------
proc dac_conf {} {

##Device configuration register write sequence
##Issue software reset
dac_spi_wr 0x0000 0x20

##Device Startup Configuration
dac_spi_wr 0x0020 0x01

## configuring to DLL INTERFACE MODE
## Turn off LSB delay cell
dac_spi_wr 0x005E 0xFE
# Select DLL configure option to freq greater thean 350MHz (500 MHz)
dac_spi_wr 0x000D 0x06
# Enable DLL and duty cycle correction.
dac_spi_wr 0x000A 0xC0
set rd_data [dac_spi_rd 0x000E]
set rd_data_hex [format "0x%08X" [expr {$rd_data & 0X000000F0}]]
if {$rd_data_hex == 0x00000080 } {
puts "DLL is locked"

##Configure Interpolation filter
dac_spi_wr 0x0028 0x80

################################### calling Reset FIFO routine
dac_fifo_reset
##############################################################
##disable Inverse SINC filter
dac_spi_wr 0x0027 0x00

#Power up DAC outputs
dac_spi_wr 0x0001 0x00

# parity fail check
dac_spi_wr 0x006A 0xE0
dac_spi_wr 0x006A 0xC0
# configuring the parity mode
dac_spi_wr 0x0009 0x21
# enabling parity fail
dac_spi_wr 0x0004 0x80

}
}

 

 

FIFO Reset Sequence:

 

proc dac_fifo_reset {} {
##Configure the DAC in the desired interpolation mode
dac_spi_wr 0x0028 0x80

set rd_data [dac_spi_rd 0x0006]
set rd_data_hex [format "0x%08X" [expr {$rd_data & 0X00000010}]]
if {$rd_data_hex == 0x00000010} {
puts "DACCLK and DCI clocks are running and stable"
} else {
puts "clocks are not stable"
}
## FIFO LEVEL CONFIGURATION REGISTER
dac_spi_wr 0x0023 0x40
##Request the FIFO level reset
dac_spi_wr 0x0025 0x01
set rd_data [dac_spi_rd 0x0025]
# set rd_data_modified
set rd_data_hex [format "0x%08X" [expr {$rd_data & 0X00000002}]]
if {$rd_data_hex == 0x00000002} {
puts "device acknowledges the request"
}
##Remove the request
dac_spi_wr 0x0025 0x00
set rd_data [dac_spi_rd 0x0025]
set rd_data_hex [format "0x%08X" [expr {$rd_data & 0X00000002}]]
if {$rd_data_hex == 0x00000000} {
puts "device drops the acknowledge signal"
}
##Read back Register
set rd_data [dac_spi_rd 0x0006]
set rd_data_hex [format "0x%08X" [expr {$rd_data & 0X00000006}]]
if {$rd_data_hex == 0x00000000 } {
set rd_data [dac_spi_rd 0x0024]
set rd_data_hex [format "0x%08X" $rd_data]
puts "read back value of fifo level read back register :$rd_data_hex"
set rd_data [dac_spi_rd 0x0024]
set rd_data_hex [format "0x%08X" $rd_data]
puts "read back value of fifo level read back register :$rd_data_hex"
set rd_data_reg24 [dac_spi_rd 0x0023]
set rd_data_reg24_hex [format "0x%08X" $rd_data_reg24]
if {$rd_data_reg24_hex == $rd_data_hex} {
puts "actual FIFO level is set to the requested level. BOTH REG ARE MATCHING"
}
} else {
puts "reconfiguring the FIFO LEVEL CONFIGURATION REGISTER"
dac_spi_wr 0x0023 0x40
set rd_data [dac_spi_rd 0x0024]
set rd_data_hex [format "0x%08X" $rd_data]
puts "read back value of fifo level read back register :$rd_data_hex"
set rd_data [dac_spi_rd 0x0024]
set rd_data_hex [format "0x%08X" $rd_data]
puts "read back value of fifo level read back register :$rd_data_hex"
set rd_data_reg24 [dac_spi_rd 0x0023]
set rd_data_reg24_hex [format "0x%08X" $rd_data_reg24]
if {$rd_data_reg24_hex == $rd_data_hex} {
puts "actual FIFO level is set to the requested level. BOTH REG ARE MATCHING"
}
}
}

 

Regards,

Erfan

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