I'm working on an application using the axi_dmac to move data between the ZC706 Zynq PS and PL. My application requires that data be held in the FPGA until read, not dropped. I switch the rfifo and wfifo for AXI Stream FIFOs and set the respective source and destination types of the dmacs to AXI Stream. I'm able to push data with both the kernel driver and the no-OS UIO program. However, with UIO I noticed in Chipscope that the data from PS -> PL is not the data from the program. I added the AXI MM Source from axi_ad9361_dac_dma to Chipscope and noticed that I lost the upper two address bits of ardata. In the synthesized design I see that the address_generator component only outputs 27 bits, ignoring the 3 unused bits due to the 64-bit bus width.
I printf'ed the physical address of the UIO memory buffer and got 0x7C420000, but with the upper bits lost, I see 0x3C420000 in Chipscope. I think this is why I'm getting bad data--the address isn't correct.
I confirmed the synthesis behavior with a clean checkout of the unmodified fmcomms5_zc706 reference design in Vivado 2016.4. The upper bits are synthesized out too.
Is this a bug or did I do something wrong with UIO program? Is there a way I can avoid this addressing issue?