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AD9528 Disabling PLL2 LDO stops clock output

Question asked by katsu on Sep 11, 2017
Latest reply on Sep 13, 2017 by pkern

Hello,

 

Setting PLL2 power-down enabled (0x0500 bit3 = 1) and PLL2 LDO disabled (0x0504 bit7 = 0), clock output from all OUTn is stopped. Could you please explain why disabling PLL2 LDO stops clock outputs?

 

I am using EVB AD9528/PCBZ (Rev. B) and AD9528 Quick Start Setup File downloaded from AD9528 EVB page (AD9528_Evaluation_BoardQuick_Start_Setup_File.stp). OUT 0,1,4,5,8,9,11,12 are set normal operation, other OUTn are set power-down. Buffer Source is set PLL1 Output for using AD9528 as a buffer of VCXO (Clock In).

 

Cases I confirmed:
PLL2 power down enabled PLL2 LDO disabled: clocks stop
PLL2 power down enabled PLL2 LDO enabled: clocks output
PLL2 power down disabled PLL2 LDO disabled: clocks stop

 

Best Regards,

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