It appears the AD421BRZ actually has a problem if the MOSI line is not brought LOW after every transmission.
This means it can be used with standard SPI, since this is not the case.
SPI leaves the MOSI bit HIGH if the last bit was “1”, and it leaves it LOW if the last MOSI bit was “0”.
My second question / problem I encounter, is that the LATCH has to be held LOW, and only brought high after 16 clocks.
But the part only knows it is regular data after two latches pulses, so LO-HI-LO and LO-HI-LO.
But if it is used in a system with other SPI devises, it has seen many different SPI Clocks, sometimes x8, sometimes x16, and even x24.
So, on the first LATCH, it may see the x16 bits that was intended for the AD421, but also the previous x8 clocks intended for some other devise.
The part then has no idea what its output should be, unless I send an additional 16 clocks, with the same data.
So it appears, the only reliable use, is to manually drive two (2) LATCH pulses, LO-HI-LO and LO-HI-LO, no Clocks, which should place it in regular mode.
The send x16 Clocks with MOSI data, one (1) LATCH pulse, manually bring MOSI Low before, during or after the LATCH pulse.
Is there a different way of making the AD421 work on a regular / standard SPI interface?
Any help appreciated