Hi,everyone ! Recently, I used a home-made AD8283 board together with original HSC-ADC-EVALCZ to capture signal. A problem was observed that when DSYNC, D0-D11,CLK+ and CLK- connected to HSC-ADC-EVALCZ, the CLK was interferd by DSYNC,and D0-D11( DSYNC,D0-D11 have fast-changing digital signals ). Becasuse of that,the data captured by VisualAnalog was in disorder.
My question is that why the clock of AD8283 was interfered when connected to HSC-ADC-EVALCZ，this is unreasonable in principle. How can I solve this problem? Call help！
(undisturbed clock of AD8283, 50MHz)
(interfered clock of AD8283 when connected to HSC-ADC-EVALCZ)
(disorganized data captured by VisualAnalog)