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ADV7511P DE generation

Question asked by psusi on Sep 7, 2017
Latest reply on Sep 22, 2017 by psusi

I managed to get the output to come on from our board, but it appears to reset every few seconds, with the output stopping, then starting back up again.  I thought that this might be because our LCD does not have a functioning DE signal. so I changed some of the registers in an attempt to get the chip to generate its own DE signal, but it did not seem to make a difference.  Have I set these registers correctly and is there any reason why the chip would keep briefly outputting a small burst of data, then stop and repeat?


0xD6, 0xC0 // force hpd on
0x01, 0x00 // Set N for 192KHz sampling and 148MHz pixel clock
0x02, 0x60 // Set N for 192KHz sampling and 148MHz pixel clock
0x03, 0x00 // Set N for 192KHz sampling and 148MHz pixel clock
0x15, 0x00 // Input 444 (RGB or YCrCb) with Separate Syncs, 44.1kHz fs
0x16, 0x60 // Output format 444, 36-bit input
0x17, 0x01 // enable DE generation
0x18, 0x46 // Disable CSC
0x38, 0x02 // 800 pixel width
0x39, 0xe0
0x3a, 0x10 // 480 pixel high
0x3B, 0xFE // Pix Rep x4
0x40, 0x80 // General control packet enable
0x41, 0x10 // power down control
0x48, 0x08 // data right justified
0x49, 0x00 // no truncation
0x4C, 0x06 // 12 bit Output
0x55, 0x00  // Set YCrCb 444 in AVinfo Frame
0x56, 0x08 // Set active format Aspect
0x96, 0x20 // HPD Interrupt clear
0x98, 0x03 // ADI Recommended Write
0x99, 0x02 // ADI Recommended Write
0x9C, 0x30 // PLL Filter R1 Value
0x9D, 0x61 // Set clock divide
0xA2, 0xA4 // ADI Recommended Write
0xA3, 0xA4 // ADI Recommended Write
0xA5, 0x04 // ADI Recommended Write
0xAB, 0x40 // ADI Recommended Write
0xAF, 0x16 // Set HDMI Mode
0xBA, 0x60 // No clock delay
0xD1, 0xFF // ADI Recommended Write
0xDE, 0xD8 // ADI Recommended Write
0xE4, 0x60 // VCO_Swing_Reference_Voltage
0xFA, 0x7D // Nbr of times to search for good phase