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AD7658 output comnparison problem

Question asked by herdinc on Sep 7, 2017
Latest reply on Sep 8, 2017 by jcolao

Hi all,

I'm using ad7658 in parallel mode. I have written my own fpga code to read the analog inputs. In simulation it works regularly but i can't see the true results at the outputs when i change it input voltage value.

In oscilloscope, the busy, cs and read signals are shown look like the simulation and true but i can't read the analog inputs. D0-D11 data aren't high z or zero, there are some values on the way. The real problem is when i change the input data up or down to 1V, there isn't any value change. The board İ have worked hasnt any uart output or sth like that so i canT observe the full data value at the same time because of this reason I preffered the comparision method.

Thnak you 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 

entity main is
Port ( clk : in STD_LOGIC; --50MHz=20ns
analog_bus : in STD_LOGIC_VECTOR (15 downto 0); --default 16 bit fakat an7658 resolution [11:0]
busy : in STD_LOGIC; --analog to digital işleminin dönüştrülmesi için gerken süre min=3us
stby : out STD_LOGIC;

led : out STD_LOGIC_VECTOR (5 downto 0);
led_b : out STD_LOGIC_VECTOR (5 downto 0);
convst_a : out STD_LOGIC; --V1 and V2
convst_b : out STD_LOGIC; --V3 and V4
convst_c : out STD_LOGIC; --V5 and V6
cs : out STD_LOGIC; --veri aktarımı sırasında 0 olmalı
rd : out STD_LOGIC; --veri aktarımı sırasında 0 olmalı
reset : out STD_LOGIC); -- veri aktarımı sırasında reset=0 olmalı

end main;

architecture Behavioral of main is
--default values
signal stby_l : STD_LOGIC := '1';
signal convst_a_l : STD_LOGIC := '1';
signal convst_b_l : STD_LOGIC := '1';
signal convst_c_l : STD_LOGIC := '1';
signal cs_l : STD_LOGIC := '1';
signal rd_l : STD_LOGIC := '1';
signal reset_l : STD_LOGIC := '1';
signal V1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal V2 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal V3 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal V4 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal V5 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal V6 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal cnt : integer range 0 to 16_777_215 ;
signal min : integer range 0 to 16_777_215 :=0;
signal busy_l : STD_LOGIC ;


type state_type is (Start_State,Wait_State, conv_a, conv_b, conv_c);
signal state : state_type := Start_State;

begin
process(clk)
begin
if(rising_edge(CLK)) then
case state is
when Start_State =>
min<= min+1;
stby_l <= '1';
if(min=0) then
reset_l <= '1';
end if;
if(min=5) then
reset_l <= '0';
convst_a_l <= '0';
convst_b_l <= '0';
convst_c_l <= '0';
state <= Wait_State;
min<=0;

end if;


when Wait_State =>
min<= min+1;
cs_l <= '1';
rd_l <='1';
if(min=50) then
convst_a_l <= '1';
convst_b_l <= '1';
convst_c_l <= '1';
end if;
if(convst_a_l='1' or convst_b_l='1' or convst_c_l='1') then
if(cnt=145) then
state <= conv_a;
cnt<=0;
cs_l<='0';
rd_l <= '0';
min<=0;
end if;
end if;

when conv_a => --convert v1 and v2
if(convst_a_l = '1') then
if(cnt=0 or cnt=1 or cnt=2 )then
rd_l <= '0';
v1<=analog_bus(11 downto 0);-- read v1 data
cnt <= cnt+1;
elsif( cnt = 3 or cnt=4 )then
rd_l <= '1';
cnt <= cnt+1;
elsif(cnt=5 or cnt = 6 or cnt=7 or cnt=8)then
rd_l <= '0';
v2<=analog_bus(11 downto 0);--read v2 data
cnt <= cnt+1;
elsif(cnt = 9 or cnt = 10 )then
rd_l <= '1';
cnt <= cnt+1;
elsif(cnt = 11)then
rd_l <= '0';
cnt <= 0;
state <= conv_b;
end if;
else
state <= conv_b;
end if;

when conv_b => --convert v3 and v4
if(convst_b_l = '1') then
if(cnt<3)then
rd_l <= '0';
v3<=analog_bus(11 downto 0);--read v3 data
cnt <= cnt+1;
elsif(cnt=3 or cnt=4)then
rd_l <= '1';
cnt <= cnt+1;
elsif(cnt = 5 or cnt=6 or cnt=7 or cnt = 8)then
rd_l <= '0';
v4<=analog_bus(11 downto 0);--read v4 data
cnt <= cnt+1;
elsif(cnt=9 or cnt = 10)then
rd_l <= '1';
cnt <= cnt+1;
elsif(cnt = 11)then
rd_l <= '0';
cnt <= 0;
state <= conv_c;
end if;
else
state <= conv_c;
end if;

when conv_c => --convert v5 and v6
if(convst_c_l = '1') then
if(cnt<3)then
rd_l <= '0';
v5<=analog_bus(11 downto 0);--read v5 data
cnt <= cnt+1;
elsif(cnt=3 or cnt=4)then
rd_l <= '1';
cnt <= cnt+1;
elsif(cnt=5 or cnt=6 or cnt=7 or cnt=8)then
rd_l <= '0';
v6<=analog_bus(11 downto 0);--read v6 data
cnt <= cnt+1;
elsif(cnt=9 or cnt = 10)then
rd_l <= '1';
cnt <= cnt+1;
elsif(cnt = 11)then
rd_l <= '1';
cnt <= 0;
state <= Wait_State;
cs_l <='1';
convst_a_l<='0';
convst_b_l<='0';
convst_c_l<='0';
end if;
else
state <= Wait_State;
cs_l <= '1';
rd_l <='1';
convst_a_l<='0';
convst_b_l<='0';
convst_c_l<='0';
end if;

end case;

end if;

end process;
busy_l<=busy;


led(0) <= not busy_l ;--3V
led(1) <= not cs_l ;--3V
led(2) <= not rd_l ;--3V

led(3) <= '0' when (v4>"000011001101") else '1';--1V
led(4) <= '0' when (v5>"000011001101") else '1';--1V
led(5) <= '0' when (v6>"000011001101") else '1';--1V

 

led_b(0) <= '0' when (v1>"000011001101") else '1';--1V
led_b(1) <= '0' when (v2>"000011001101") else '1';--1V
led_b(2) <= '0' when (v3>"000011001101") else '1';--1V
led_b(3) <= '0' when (v4>"000011001101") else '1';--1V
led_b(4) <= '0' when (v5>"000011001101") else '1';--1V
led_b(5) <= '0' when (v6>"000011001101") else '1';--1V


convst_a <= convst_a_l ;
convst_b <= convst_b_l ;
convst_c <= convst_c_l ;
cs <= cs_l ;
rd <= rd_l;
reset <= reset_l;
stby <= stby_l;

end Behavioral;

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