I am attempting to synchronize two parallel HMC7043 evaluation boards that are being driven from the same clock source. I get very inconsistent results from the outputs of both of my HMC7043 devices.
I have verified that my input signals, both system clock and the SYSREF pulses are consistently aligned and meet the JESD204B spec. I have included a screen capture of both CLKIN and RFSYNC inputs for reference.
I have also included a couple screen captures of the results I am seeing. One of my devices seems to perform consistently, where the other does not. I have them both configured the same and am loading the same .py file to both.
I am using LVPECL output buffer, with 150 ohm termination resistors to ground on both the CLK and SCLK outputs. My CLK outputs are divide by 1, so I have a digital step of 1 applied to ensure phase alignment. My SCLK outputs are divide by 12, but also have the digital step of 1 applied for consistency. I have the dynamic output buffer disabled, as I notice very inconsistent outputs with this feature active. I have the SYNC retime MUX set to retime, and my SYSREF timer is currently set to 13.
Is there something drastic I am missing with this setup? Thanks for any help with this issue, I can provide more details if needed.