I have a customer using the FMCDAQ2 board as a reference for their design. In the default, both the AD9144 DAC and the AD9680 ADC run at a sample rate of 1GSPS on this board, when working with the eval software, as is.
The customer wants to run the DAC at 750MSPS, and has successfully done so. The next step is to turn on the 2x interpolation filter on the DAC, which means the sample rate out of the JESD interface will now be 375MSPS.
I understand that the JESD core in the FMCDAQ2 reference design is an ADI design, not just an incremental change to the Xilinx designed FPGA core. My question is, can this JESD core be run as is, without the FPGA core being recompiled. Can this be done in software, by just changing the register writes called by the C code, or does the FPGA need to be recompiled.