AnsweredAssumed Answered

AD9361 No-Os Driver TDD Pin Pulse Mode

Question asked by ruhen on Sep 6, 2017
Latest reply on Sep 11, 2017 by Vinod

Hello. I am using the AD9361 and had a functioning design with both RX and TX in FDD mode. I am trying to switch the design to TDD pin pulse mode by doing the following in the NO-OS driver:

 

Set "//frequency_division_duplex_mode_enable *** adi,frequency-division-duplex-mode-enable" from 1 to 0

Set both "//ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable" and 

"//ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable" from 0 to 1

 

I implemented signals generated on both the ENABLE and TXNRX pins according to the UG-570 AD9361 Reference Manual Figure 10: Enable Pulse Mode, TDD. I have probed the test points on the FMCOMMS2 board and they are behaving identically as the diagram shows. However, I am no longer seeing and TX data. Is there another setting init_param that I need to change to allow TDD mode to work? Or is there a minimum time needed in the alert state other than the ~6 clock cycles depicted in the figure?

Outcomes