Again, more on an observation. In the ‘PLL1 Reference Clock Inputs’ on page 23 of the AD9523-1 datasheet (rev C), I am told to set bits 5 and 6 of register 0x01A to enable single ended mode. This disagrees with Table 40, which indicates that bits should be cleared for single ended mode. After some experimentation, I believe that page 23 is correct and Table 40 is incorrect. Do you agree?