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AD9523-1 reference inputs

Question asked by EdCooper on Sep 6, 2017
Latest reply on Sep 8, 2017 by pkern

Again, more on an observation. In the ‘PLL1 Reference Clock Inputs’ on page 23 of the AD9523-1 datasheet (rev C), I am told to set bits 5 and 6 of register 0x01A to enable single ended mode. This disagrees with Table 40, which indicates that bits should be cleared for single ended mode. After some experimentation, I believe that page 23 is correct and Table 40 is incorrect. Do you agree?