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AD9910 REFCLK divide-by-two

Question asked by jordens on Sep 5, 2017
Latest reply on Sep 10, 2017 by mcee


The discussion in AD9910 PLL Multiplication Value - Results is 1/2 of Expected  concluded with the statement that the REFCLK divide-by-two (controlled by CFR3[15]) is in fact in the path to the PLL. This conflicts with  AD9910 datasheet, figure 30 which shows the divide-by-two in the path that bypasses the PLL.


Question 1: Which is that correct?


Question 2: If the divide-by-two is in front of the PLL, can one drive REFCLK with 100 MHz, use the divide-by-two to feed the PLL with 50 MHz, and use a 20 PLL divider to get a 1000 MHz clock for the AD9910?


Best regards,