with your help and support specially from Istvan, Lars and Rejeesh, I got the FMCDAQ2 R2017_r1 hw with NoOS sw (dev branch) on KC705 board working with all possible ADC sampling rates (1000Mhz, 600Mhz, 500Mhz and also 300Mhz) .
Now I will plug my Design between AD9680_core and the AD9680_cpack, using the 300Mhz ADC sampling rate.
The bus is 64bits 4 samples wide (channel I) and 4 samples (channel Q). I would like to now the frequency of adc_clk
I suppose it's the adc_fpga_clock, which means 300Mhz/4 ?? in this case the adc_valid signal is an active high continous signal, is this right ?
thanks again for your help