I am looking to develop a system to integrate a C-RAN base station where i need to receive the streaming samples from the Ethernet port, perform the Inverse Fourier Transform and then send them to DAC to be transmitted. The DAC writing is performed with the No-OS device driver and the data is captured with aid of LWIP. So this raised a few questions regarding DAC operation:
1) After dac_init() can i update the samples by simply writing on DAC_DDR_BASEADDR memory area?
2) The FFT IP Core can be inserted in the HDL Design?
3) If so, the correct place is between DAC_UPACK and DAC_FIFO cores?
I would apreciate if someone could help me, thank you in advance.