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SPI Communication Issue with AD7264

Question asked by UtpalT on Sep 1, 2017
Latest reply on Sep 7, 2017 by UtpalT

Good morning.

 

We are using AD7264 in our design.

AD7264 is interfaced with iMX6 NXP Processor.

 

We would be grateful to have any insight on the queries detailed.

 

Scenario:

Validating SPI Communication with AD7264

 

Queries

  1. Is there a specific initialisation sequence for AD7264?
  2. Does there exist a reference code for initialisation?
  3. Can internal registers be read from / written to without doing any calibration?
  4. Data is transferred to AD7264 in a packet of 8 bits. An idle period of 4.5 uSec is observed between two byte transfers. Will it affect SPI communication? (Please refer image AD7264_SCLK_TimeDelay.BMP)
  5. Is there a max. time delay acceptable between transfer of successive bytes?
  6. How critical are DIN setup time (3 nSec min.) and DIN hold time (3 nSec min.)? In our case, setup time is 0 and hold time is one SCLK cycle.

 

Steps carried out & observations:

  1. Read contents of ADC A Internal Offset Register after power-on.
    (All "0" as suggested in datasheet Page # 23)
  2. WRITE a known value (NOT CALIBRATION VALUE).
  3. Read contents of ADC A Internal Offset Register.
    All "0". Expected is the written known value.
  4. Carry-out (1) to (3) for
    1. ADC B Internal Offset Register
    2. ADC A External Gain Register
    3. ADC B External Gain Register
      Results are the same as in case of ADC A Internal Offset Register.

 

Checks Performed

Checks PerformedObservations
Chip select polarity

Idle high

Active low during transmission

SCLK polarity

Idle high

Active low during transmission

Chip select to SCLK setup time

12 uSec

Required is 10 nSec min. (Datasheet Page # 29)

SCLK frequency

1 MHz

MOSI Data stream on AD7264 PD0/DIN pin

Expected data stream as per the WRITE / READ scenarios

MOSI data transfer w.r.t SCLK

Bits are transferred on "falling edge" of SCLK

AVcc

5 V

Vdrive5 V
Vref2.5 external

 

Bit Streams used

RequirementBit stream
ADC A Internal Offset Reg. Read

(MSB) 0001 0010 0001 0001 0000 0000 0000 0000 (LSB)

Last 20 LSBs are to generate SCLK for data receiving

ADC A Internal Offset Reg. Write

(MSB) 0010 0101 0101 0101 0000 (LSB)

b15-b4 : dummy data 0x55 to validate read operation

 

Best regards,

-- Utpal

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