We desire an effective data output rate of 625kHz for each of our data channels.
We would like to achieve that using four AD7768 channels, each sampling at 625kHz/4 but phased such that the composite sampling rate of the four channels is 625kHz.
Our initial experiments seem to indicate that the samples are not interleaved at the input, but are delayed at the output. In other words, the 4 parallel channels are being sampled (and held) simultaneously instead of one at a time as we assumed given the device documentation.
How does CHX_SYNC_OFFSET work?