I am using AD9625, when I use 4 lanes 1GSPS, it is normal, however when I use 8 Lanes 2.4Gsps, FPGA shows that it could not lock.
Could you please help check above issue.
Are you changing the FPGA load/configuration when you change from 4 lanes to 8 lanes? This sounds like an FPGA timing problem, not a problem with the ADC.
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