I have a question about logic levels for AD6688 SINCINB+/SINCINB- inputs and FPGA Artix 7 outputs.
DRVDD1 = 0.975V. Datasheet says that we can drive SINCINB using LVDS or CMOS.
But Artix 7 FPGA has next LVDS_25 specifications:
and LVCMOS18 specifications:
And I see that some LVDS_25 and LVCMOS18 specifications don't correspond to SINCINB+/SINCINB- specifications.
I can use DIFF_HSTL and DIFF_SSTL standards:
But I need additional VTT regulator to realize it:
Please correct me if I wrong.