AnsweredAssumed Answered

Chipscope on hdl/projects/daq2/kcu105

Question asked by cswanson on Aug 31, 2017
Latest reply on Sep 13, 2017 by AdrianC


I would like to use Vivado Chipscope on the hdl_2016_r2 for the daq2 kcu105 board.  The signals I would like to probe are the control signals on the HPC connector to the DAQ2 board.  Utilimately I would like to use SDK to step through the driver C code and watch the signals change on the HPC.  I would like to understand JESD204B operations on the DAQ2 card and possibly eliminate the Microblaze and replace with state machine fpga logic that does the same thing as the drivers.  I don't know if it doable, and if it is not, then I still would like to study the driver interaction with the DAQ2.


I have started to add debug signals in the synthesis phase of Vivado to probe the following signals in system_top.v:

(* mark_debug = "true" *) inout [16:0] gpio_bd;

(* mark_debug = "true" *) inout [16:0] adc_fdb;

(* mark_debug = "true" *) inout [16:0] adc_fda;

(* mark_debug = "true" *) inout [16:0] dac_irq;

(* mark_debug = "true" *) inout [16:0] clkd_status;

(* mark_debug = "true" *) inout [16:0] adc_pd;

(* mark_debug = "true" *) inout [16:0] dac_txen;

(* mark_debug = "true" *) inout [16:0] dac_reset;

(* mark_debug = "true" *) inout [16:0] clkd_sync;


Then I follow the procedure in the Ettus app note Debugging FPGA images.  In the app note, it says to interrupt the synthesis cycle and insert the debug core for the above signals.  I have attached the app note.  In the case for hdl, I will run "make -C projects/daq2/kcu105 and let it finish.  Then open up the project and insert the above debug signals and then generate the bitstream just like the app note.


But when I tried this, I believe I saw timing errors in the report.  Am I missing something?  Shouldn't I be able to use Chipscope to watch the SDK drivers toggle my signals in Chipscope and meet the same timing?