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[AD9361]how to shorten the latency between ENABLE pulse and the presentce of the first data sample

Question asked by 西门吹猫 on Aug 30, 2017
Latest reply on Sep 8, 2017 by Vinod

Hello~

I want to use the AD9361 to implement WIFI data frame transceiver.My Interface Mode is CMOS、DDR、SinglePort,data_clk  is 40MHz.

We use pulse mode to control the AD9361 ENSM.When the ENSM goes to the TX state from the ALERT state.

If we wait 9us to preserent the first data sample, the transmit EVM can be -35dbm(BPSK modulation).

If we shorten it to 6us, the EVM goes down to -27dbm。

Then I used agilent VSA to demod the AD9361 RF transmit signal.Found that at the beginning of each Frame,there is a slow rising lasting about 10us in time domain( shown below).

My Question is

What can cause the slow rising?

How to make the rising time at the beginning of the frame shorter(2us is the best ) 

 

Thanks a lot!

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