AnsweredAssumed Answered

AD9680-1000, SYSREF transition not detected

Question asked by Stefan_G on Aug 25, 2017
Latest reply on Sep 15, 2017 by UmeshJ

I am trying to synchronize across multiple ADCs using SYSREF. In my test setups, I have 3 ADCs, and I am able to successfully synchronize 1 and 3 together, as verified using the ramp test output; the ramp outputs of ADC1 and ADC3 are in lock step as verified by a data capture in my FPGA after all the samples have been sent through the JESD interface. However, I cannot get ADC 2 to synchronize with the others.


After identical configuration of all ADCs, and samples are flowing through the JESD interfaces to the FPGA successfully, I do the following:

  1. Set SYSREF_CNTL1 (0x120) in all 3 ADCs to 0x04, arming them in N shot mode.
  2. Set SYSREF_CNTL2 (0x121) in all 3 ADCs to 0x00, setting sensitivity to the next SYSREF pulse only.
  3. Generate a single, simultaneous SYSREF pulse to all 3 ADCs.


And then I observe the following behavior.

  1. SYSREF_CNTL1 (0x120) is now cleared to 0x00 on ADC1 and ADC3, but it remains 0x04 on ADC2.
  2. The LMFC signals of ADC1 and ADC3 are now synchronized to each other, but not to the LMFC signal of ADC2 (I am outputting them on the FD_B pin for debug)


Debug status so far.

  • Vpp of CLK+/- is 1.14 V @ 866.67 MHz
  • Vpp of SYSREF+/- is 1.25 V, pulse length of 150 ns (exactly 130 CLK+/- periods)
  • CLK+/- varies by < 25 ps between ADCs
  • SYSREF+/- pulse varies by < 25 ps between ADCs
  • All other ADC and JESD operation is good/normal.
  • SYSREF_STATUS (0x128) reads back 0x80 for ADC1 and 0x88 for ADC3. These setup/hold times are acceptable according to the data sheet. I originally tuned these setup/hold times using a continuous SYSREF generated by my PLL (LMK04828) and then go to a single pulse for the real system application.
  • During the setup/hold tuning stage, I would continuously output SYSREF+/- pulses at 6.67 MHz (866.67/130 MHz) and after setting the N-shot mode (setting 0x120 to 0x04) the register is cleared back to 0x00 for all ADCs, and the SYSREF_STATUS for all ADCs updates with apparent valid setup/hold times also. So, it appears that ADC2 is capable of detecting a SYSREF+/- transition, but needs 100s or 1000s before doing so?
  • I have also tried all combinations of the CLK+/- edge select and SYSREF+/- transition select in 0x120 with the same results.


Finally, on another identical test board, I am observing a slightly different behavior. On that system, I am also able to synchronize 2 of the ADCs (ADC2 and ADC3 in this case) but, when I write SYSREF_CNTL1 (0x120) of ADC1 to a 0x04, it either does not take (unlikely) or is immediately cleared (more likely) to 0x0 (by a false SYSREF detection?) even though I have not generated a pulse on the SYSREF+/- pins.