This is a continuation on discussion AD9144 and Libiio - How to Clear the Buffer?
Yesterday, your team solved the problem of clearing the buffer on linux (git commit c352b21d2354d0e198c1a5da5b351682ae80e986 on branch 2016_R2:dbogdan microblaze: dts: vc707_daq2: Enable the PL FIFO for TX) by modifying the corresponding devicetree.
My next question was the buffer size. It was mentioned that for now, it is configured to be 16K bytes. This configuration is set in the HDL code for AD9144 (/hdl/projects/daq2/vc707/system_bd.tcl) which reads:
p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
It was mentioned that p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 is setting the buffer size to be 128 * 2^10 bits = 16K bytes. daq2: zc706: Increase DAC FIFO size · analogdevicesinc/hdl@db459d9 · GitHub suggests to increase 10 to say 16 to increase the buffer size.
So I wanted to give it a try and see if I can increase the buffer size. Since, the zip file sent to me on the AD9144 and Libiio - How to Clear the Buffer? discussion was a compiled version of HDL code (system_top.bit) and a compiled version of IIO linux (simpleImage.vc707_fmcdaq2), I decided to recompile the HDL code (regenerate system_top.bit) with the same settings as 2^10 bit buffer depth (reproducing the same bitstream) and if it works then I would change it to say 2^16 bit and recompile.
So this is what I have done:
$ cd hdl
Since the compiled buffer-cleaning-corrected linux version was 2016_r2, I tried to compile the HDL code on the master branch (which was merged from hdl_2016_r2) since I assumed they need to be compatible:
$ make daq2.vc707
Resulted in the following error (logged in the /hdl/library/axi_ad9144/vivado.log file):
# adi_ip_create axi_ad9144
ERROR: This library requires Vivado 2016.2.
I am using Vivado 2017.2. Following some suggestions on the web, I tried to change the following two files:
/hdl/library/scripts/adi_ip.tcl: set REQUIRED_VIVADO_VERSION "2017.2"
/hdl/projects/scripts/adi_project.tcl: set REQUIRED_VIVADO_VERSION "2017.2"
This changed made compiling the library successful, but the project compilation stopped with the following error message (logged in the hdl/projects/daq2/vc707/vivado.log file):
ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:ip:microblaze:9.6
Searching for such error, it was mentioned that IP configuration is different from Vivado version to version. But I really do not want to downgrade my Vivado to 2016.2.
Next step I did, was to checkout "hdl_2017_r1" branch:
$ cd hdl
$ git checkout hdl_2017_r1
Although the required Vivado version for both scripts is set to "2016.4", it completed the compilation without errors:
$ make daq2.vc707
Resulted in the bitstream file /hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/system_top.bit.
So I programmed the FPGA using this bitstream and downloaded the compiled 2016_r2 linux version on the microblaze (which correctly clears the buffer):
XMD% fpga -f system_top.bit
XMD% connect mb mdm
XMD% dow simpleImage.vc707_fmcdaq2
XMD% disconnect 0
The microblaze recongnizes the DAQ, since if I ssh to the linux and ls the /sys/bus/iio/devices/ I see the devices. Using my program (or iio-oscilloscope), if I change any settings (like changing single tone frequency, scale, etc. ), I can see the changes reflected on the microblaze linux. However, I get no output from the DAC.
I though this should be a miss match between "hdl_2017_r1" and the "linux 2016_r2". Is that correct?
Is it possible to update one of the HDL branches to be compatible with Vivado 2017.2 and the linux c352b21d2354d0e198c1a5da5b351682ae80e986 commit?