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Can't lock HMC832 to 80MHz output with low PFD frequency

Question asked by dantheflyinman95 on Aug 24, 2017
Latest reply on Aug 30, 2017 by dantheflyinman95

Hello,

I am using the attached register file with an HMC832 PLL in an attempt to lock an 80 MHz reference input to an 80 MHz output. I'm trying to get the PFD frequency to 10 kHz (as low as possible) so that I can test oscillators for micro-jumps. Having a low PFD frequency increases the time to lock, which is what I want, however my PLL never locks to 80 MHz with the attached register file, and rather hovers around 82 MHz.

 

Below are the outputs I get when varying the divider parameters:

 

  • R-divider = 8000, N-divider = 288000, VCO output divider = 36  --> 82 MHz output
  • R-divider = 100, N-divider = 3600, VCO output divider = 36        --> 82 MHz output
  • R-divider = 50, N-divider = 1800, VCO output divider = 36          --> 80 MHz output
  • R-divider = 1, N-divider = 36, VCO output divider = 36                --> 80 MHz output

 

Any advice as to how I can get the HMC832 to converge to an 80 MHz output with the PFD Frequency at 10kHz would be much appreciated! 

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