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I/Q Phase Imbalance (Not working RX Quadrature Tracking)

Question asked by fischer on Aug 24, 2017
Latest reply on Sep 25, 2017 by fischer

Our Problem:
We have a distortion along the 45° axis in the i/q diagram. This is typical for i/q phase imbalance.
We use the monitor input and sample an un-modulated carrier frequency (CW) transmitted from the TX output. So we measure the phase change in the channel from TX output to monitor input.
Problem Solving 1 (Not working):
Using the RX quadrature tracking function should minimize the phase imbalance. But in our setup the RX quadrature tracking algorithm doesn’t converge. When the RX gain and phase registers (0x170 and 0x171) are probed, we read permanently changing register values up to the highest order position.
Question 1:
Are there any specified prerequisites necessary for a converging RX tracking algorithm?
Question 2:
When the tracking is disabled and the force bits for phase and gain are set, a constant value for phase is shown (0xD5). Is this a factory calibrated initial value for the RX path? Probably this value is not adequate for the monitor path. Because even when we write this value in the phase register with force bit set afterwards, the distortion along the 45° axis remains.
Problem Solving 2:
We deactivated the tracking algorithm and searched for a constant phase offset value (register 0x170) to get a minimized distortion in 45° direction. Afterwards we had only left a distortion in 0° direction, typical for i/q gain imbalance. Then we searched for a constant gain offset value (register 0x171) to get a minimized distortion in 0° direction.
The DC offset values read in registers 0x174-0x176 are stable despite a non-converging Rx tracking algorithm. So we did a one-time read of this values with activated tracking.
Now in our program routine we write at startup the constant phase, gain and DC offset values into the proper registers and set the force bits afterwards (without releasing them).
Question 3:
Is the procedure in "problem solving 2" generally correct? Are this phase and gain offset values equal for each AD9361 chip? How much are this values changing over temperature, frequency and gain change?


Question 4:
What are the typical phase [in degree] and gain [in dB] imbalance values for the AD9361 when using the monitor input?