Can I clock the AD5664 32 times, and have just the first 24 bits work properly? I need to share the SPI interface with another device, which will work if the DAC accepts 24 bits and ignores the rest.

On the data sheet, fig 29, the output amp is shown as having a gain of 2. That seems inconsistent with the equations. If I use a reference of +4 volts, what will the maximum output be?

The data sheet, rev 0, is 11 years old. Is rev 0 a preliminary draft?

Incidentally, it's very hard to find the place to post a question to this forum.

Hi jjlarkin,

Based on the data sheet description, the shift register will only accept the first 24 bits and ignore the other 8 bits once the SYNC pin is pulled high, so the AD5664 should work with the 32 bit sequence.

The external reference voltage is actually divided by 2 inside the chip so the +2 gain of the output buffer is just cancelled out and the computation for the output voltage will still be the same. VOUT=VREFIN x (D/2^n).

The Rev.0 AD5664 data sheet is not a preliminary data sheet and has not been revised since it was released.

Best regards,

Rainier