I am doing static timing analysis on the I2C interface of the ADV7180 to a Xilinx SoC. Most of the timing parameters I need are provided in the ADV7180 datasheet, except for data output hold time.
In other device datasheets, I have seen this parameter referred to as "clock to data delay time" or "output valid from clock" and is typically specified as 900nsec max.
The closest spec in the ADV7180 datasheet is "Hold Time (Start Condition)" at 600ns min, but the max is not specified, and this is specifically calling out the start condition, not the "normal" condition.
Any help or suggestions would be appreciated.