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AD9914 direct mode and sync_clock

Question asked by ChristopheMe on Aug 23, 2017
Latest reply on Aug 30, 2017 by mcee


I am using an AD9914 evaluation board linked to a Xilinx Virtex5 FPGA.

I can read and write registers in parallel mode (F=”0000”) and use the AD9914 in profile mode with success.

My goal is to use it in direct mode and I am encountering some problems.

When I switch in mode F=”0010” and I put a constant frequency on the data bus (D[31..0]) it works.

But as soon as I change the frequency, the AD9914 goes in a strange mode and only a reset can make it works again: the SYNC_CLK change from 100MHz to 1MHz and I cannot change the frequency anyway.

Could you please help me to solve this problem?

I suspect that the data change (D[31..0]) don’t respect the 2ns timing before SYNC_CLK. So I am changing the data only every 6 SYNC_CLK periods and rise the IO_UPDATE signal for 2 SYNC_CLK periods 2 SYNC_CLK period after the data change, so I am sure data are stable 1 period before the IO_UPDATE signal (see attached picture).




My registers configuration is:

// CFR1

   // <Register Address="00" Data="00010008" />

   WriteDDSReg(    0x00,   0x08     );

   WriteDDSReg(    0x01,   0x00     );   

   WriteDDSReg(    0x02,   0x01     );

   WriteDDSReg(    0x03,   0x00     );

   // CFR2

   // <Register Address="01" Data="00800900" />

   WriteDDSReg(    0x04,   0x00     );

   WriteDDSReg(    0x05,   0x09     );

   WriteDDSReg(    0x06,   0x80     );

   WriteDDSReg(    0x07,   0x00    );

   // CFR3

   // <Register Address="02" Data="0004781C" />

   WriteDDSReg(    0x08,   0x1C     );

   WriteDDSReg(    0x09,   0x78     );

   WriteDDSReg(    0x0A,   0x04     );

   WriteDDSReg(    0x0B,   0x00     );

   // CFR4

   // <Register Address="03" Data="00052120" />

   WriteDDSReg(    0x0C,   0x20     );

   WriteDDSReg(    0x0D,   0x21     );

   WriteDDSReg(    0x0E,   0x05     );

   WriteDDSReg(    0x0F,   0x00     );

   // Digital ramp lower limit

   WriteDDSReg(    0x10,   0x00     );

   WriteDDSReg(    0x11,   0x00     );

   WriteDDSReg(    0x12,   0x00     );

   WriteDDSReg(    0x13,   0x00     );

   // Digital ramp upper limit

   WriteDDSReg(    0x14,   0x00     );

   WriteDDSReg(    0x15,   0x00     );

   WriteDDSReg(    0x16,   0x00     );

   WriteDDSReg(    0x17,   0x00     );


   // Profile 0: frequency

   // <Register Address="0B" Data="0AAAAAAA" (99.99999962747 MHz)

   WriteDDSReg(    0x2C,   0xAA     );

   WriteDDSReg(    0x2D,   0xAA     );

   WriteDDSReg(    0x2E,   0xAA     );

   WriteDDSReg(    0x2F,   0x0A     );

   // Profile 0: phase / amplitude

   // <Register Address="0C" Data="00000000" />

   WriteDDSReg(    0x30,   0x00     );

   WriteDDSReg(    0x31,   0x00     );

   WriteDDSReg(    0x32,   0xff    );

   WriteDDSReg(    0x33,   0xff    );

And to switch in direct mode:

      WriteDDSReg(0x06, 0x40); // disable profile mode and enable parallel mode