Hi,

I'm trying to determine the maximum signal bandwidth possible for a given JESD204B configuration (L-M-F).

For example, lets look at JESD204B Mode 1 (dual link).

I've attached below Table 13&20, specifying the Data structure and JESD204B configuration.

As i understand, M=4 means i have four complex converters, two for each DAC:

DAC0_Ch0 = I0+jQ0 ; DAC0_Ch1 = I1+jQ1

DAC1_Ch0 = I2+jQ2 ; DAC1_Ch1 = I3+jQ3

DAC0_Ch0 = I0+jQ0

I'm not sure I'm fully understanding the question. If you have an FPGA baseband data rate of 200MHz that is what it will be even after deserialization. The lane rate in the configuration you mention will be as follows:

Lane rate = (10/8) * 16 * 200MHz * (4/2) = 8Gbps is the lane rate (per lane, there are 2 lanes per link in this configuration so 4 lanes total if you are running dual link to use both DAC 0 and DAC 1). This is just the lane rate though, this is not the true data rate - this takes into account the encoding etc for what the lane rate needs to be in order to provide a 200MHz data rate.

Therefore if the true data rate is 200MHz, then the available bandwidth is up to 80% of the data rate Nyquist (data rate Nyquist is half the data rate, so 100MHz) which would be 80MHz real, or double that 160MHz complex if you're sending DC centered data.

You can see that the table says the max data rate for Mode 1 is 385MHz. This is because the maximum lane rate for the part overall is 15.4Gbps. Therefore by back-calculating what this would be for a data rate you get:

Max Data Rate = (8/10) * 1/NP * Max Lane Rate * (L/M) = (8/10) * (1/16) * 15400Mbps * (2/4) = 385MHz

This means you can generate each of the I and Q data streams in the FPGA at 385MHz for each of the 2 channels for both DACs at this rate and maintain that data rate after the serialize/deserialize stages with this part.

Hope this clarifies things more.