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AD9361 Data Loopback Verification

Question asked by Jmg0815 on Aug 22, 2017
Latest reply on Aug 24, 2017 by Vinod

With the AD9361 configured for data loopback test (configuration: LVDS, DDR, 2R2T, Dual Port, Full Duplex),  the received channel 1 data from the AD9361 is correctly received, but the received channel 2 data is always 0. The channel 2 transmit data from the AD9361 has been verified by configuring the AD9361 to generate the BIST tone. When the AD9361 is configured for data loopback test mode are the receive port data, frame and clock signals routed directly to the transmit port of the AD9361 or is there a dependency based on the configuration?