I have two questions.
I want to align the I/O_UPDATE signal with SYNC_CLK on an AD9914. I know how to do this and have done it successfully with AD9959 chips. In that case I used two sections of a 74LVC74 D Flip-Flop with 3.3 Vdc power, with the I/O_UPDATE pulse on the D input of the first flip flop and the SYNC_CLK on both clock inputs. I tried doing the same with the AD9914, but the amplitude of the SYNC_CLK signal is too low, about 1.8 V maximum. I think I can make the circuit work if I reduce the Vcc to 1.8 V, but then I will have an output signal that is too low for the 3.3 V logic input of the AD9914.
So the first question is: How do I align a 3.3 V I/O_UPDATE signal with the 1.8 V SYNC_CLK signal and get a 3.3 V logic signal out.
I was planning on using an AD9914 to generate a signal at 2856 MHz using a reference clock frequency of 3.5 GHz. This actually works fine, except that I need two signals that are synchronized. I don't care about the absolute timing, but I need the two outputs to have the same phase difference every time I turn the system on. I am now reading that it is not possible to synchronize two AD9914s with a 3.5 GHz clock.
So the second question is: Will I be able to synchronize the AD9914s if I lower the clock frequency to 2.5 GHz? I will be able to get my 2856 MHz signal from the alias fo+fref, by setting fo to 356 MHz.