Is there a way to simulate the PLL response specification of AD9548?
I'm trying to find out the best filter configuration for my application. As the bandwidth of the loop filter in AD9548 is low, it took me a long time to try a group of settings on the eval board each time, and it's difficult to record and plot the test result.
I tried to build a simulation model, but I couldn't figure out the model of the TDC and PFD because it's not mentioned in the datasheet how this module is implemented. Do you have any solution to this problem? Or is there a simple system function that describes the response specification of the DPLL?