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AD9361 DATA timing

Question asked by KKkk Employee on Aug 22, 2017
Latest reply on Aug 22, 2017 by KKkk

Hi, 

I found below description in ADI website: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/interface_timing_validation

The FMCOMMS[2345] boards featuring AD9361 has a digital tuning feature (programmable IO delay) and in most cases the FPGA features programmable IO delay elements as well. The software tunes this interface for an optimal delay setting ensuring that the interface works over part to part variations (AD9361 and the baseband/FPGA), voltage, temperature, interface speeds and across different carrier boards (trace differences in PCB layout).

The tuning may be done either in FPGA, AD9361 or both (though not necessary). The FPGA tuning may be the preferred option for you, as it can compensate for the high fan-out clock buffers, however, since not all FPGA devices have this option - in the ADI reference designs and software - we don't use the FPGA, and stick with the AD9361 tuning only.

My question is which Reg used for tuning the delay in AD9361?

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