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How do I configure the AD9208-3000EBZ to sample real data using both ADC cores?

Question asked by johnsja.dynetics on Aug 21, 2017
Latest reply on Sep 6, 2017 by UmeshJ

I am evaluating the AD9208 using the AD9208-3000EBZ and the ADS7-V2EBZ carrier board. I am using the ACE software to interface with the hardware.

 

I would like to sample from channel A and channel B simultaneously in full bandwidth mode. The Initial Configuration Summary is as follows:

Clock Input: 5.4GHz

Clock Divide Ratio: Divide by 2

Chip Operating Mode: Full bandwidth mode (High Performance Mode)

Chip Q ignore: Both Real (I) and Complex (Q) Selected

Chip Decimation Ratio: Full Sample Rate (Decimate by 1)

(Fadc) ADC Clock Frequency: 2.7GHz

(Fout) Output Frequency: 2.7GHz

(L) Lanes: L=8

(M) Virtual Converters: Link connected to Two Converters (M=2)

(F) Octets per Frame: F=2

(N') Bits per sample: N'=16

Lane Line Rate: 13.5Gbps

Ref Clock: 675MHz

 

How do I configure the ACE software/Evaluation Board to sample channel A and channel B simultaneously and display both channels in the Analysis tab simultaneously?

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