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Changing ADC sample frequency FMCDAQ2 R2017_R1

Question asked by cerasic on Aug 20, 2017
Latest reply on Sep 1, 2017 by larsc





I got the FMCDAQ2 R2017_R1 + NO-OS dev working with  DDS as source DATA, ADC and DAC are sampled at 1Ghz,


I have changed the register Clock devider register 0x10B of AD9680  (=0x01)  to devide  the sampling frequency of the ADC by 2, when I capture the Data from the DRAM, it is equal to zero, I tried to change also  ad9680_param.lane_rate_kbps = 10000000;  (putting 5Gsps instead), It didn't work also .. May be you have not checked that. Since I use the latest NO-OS dev which is not released yet, I can expect that, this soft is still not mature. My objective is to sample the ADC with mimimum  sampling clock possible, I think 300 Mhz according to the datasheet. Please can you tell me how to proceed giving me kindly the list of registers I have to set .. thanks for your help, many thanks to all of you for your great support specially Istvan, Lars and Rejeesh .;


Best regards, Daoudi