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HMC987 minimum jitter output

Question asked by Agd on Aug 17, 2017
Latest reply on Jun 17, 2018 by Agd

Hi,

 

I am trying to minimize the clock jitter added by the HMC987 fan-out chip and have a liberty to chose outputs (not all 8 are used in the design). A quick measurements of the time domain (not bandwidth limited) jitter using the evaluation boards show some variations:

 Input, 315
 1, 452, good, 
 2, 439, best
 3, 402, best
 4, 455, good,
 5, 471, fair,
 6, 465, fair,
 7, 469, fair,
 8, 445, good
The "best" outputs 2 and 3 are the closest to VCCA, but 6 and 7 close to VCCB are among the worst ones.
Do you have any suggestions?
Regards,
Alex

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