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ADE7880 CRC32 CHECKSUM

Question asked by hcls on Aug 17, 2017
Latest reply on Aug 25, 2017 by hcls

Hi,

 

I'm currently trying to verify the CRC computation for ADE7880 to compare the result with the CHECKSUM register 0xE51F.

The datasheet says:

The registers covered by this register are MASK0, MASK1, COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN, CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG, all registers located in the DSP data memory RAM between Address 0x4380 and Address 0x43BE, and another eight 8-bit reserved internal registers that always have default values.

And the total number of bits should be 2272.

 

I figured that:

  • the MASK0, MASK1, COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN, CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG account for 208 bits.
    • MASK0 and MASK1 are both 32 bits
    • COMPMODE, GAIN, CFMODE, CF1DEN, CF2DEN, CF3DEN, CONFIG are all 16 bits
    • MMODE, ACCMODE, LCYCMODE, HSDC_CFG are all 8 bits
  • All registers located in the DSP data memory RAM between Address 0x4380 and Address 0x43BE (= 63 registers of 32 bits = 2016 bits)
  • eight 8-bit reserved internal registers : 64 bits

with a total of (32*2 + 7*16 + 4*8) + 63*32 + 8*8 = 2288 bits, which is not equal to 2272 bits : 16 additional bits.

 

My questions are:

  • Is there something wrong in my understanding of the registers and sizes to use in the CRC ?
  • Is the value of the eight 8-bit reserved internal registers always 0 ?
  • What are the register addresses for those eight 8-bit reserved internal registers ?

 

Thanks a lot !

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