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ADV212 data of CODE FIFO all 0s

Question asked by K_sy@foxmail.com on Aug 14, 2017
Latest reply on Sep 7, 2017 by K_sy@foxmail.com

Dear Mr or Mrs

I am using microblaze to configurate ADV212 in raw pixel mode,after checking SWFLAG=0XFF82,clear EIRQFLG      and then send pixel to VDATA ,I use 16bit host mode to read fifo ,after IRQ=0  and EIRQFLG[1]=1,I begin to read fifo,but all data are 0s,SCOM[3:0] repeat  7-A-B-C,nut no  8,how can i solve this problem?MCLK=40M ,VCLK=40M,I have written VSTRB/VRDY/VFRAM timing in  Verilog according to figure 28 in programmingguide,but I am not sure the meaning of them,when the VDRY will become 0(according to my test ,VRDY will become 0 after about 2900 pixels) ?can you give me a  exact timing? Thank you!

PLL_HI       <- 0x0008

wait4 20us

PPL_LO       <- 0x0084

wait4 20us

BOOT         <- 0x008a

wait4 20us

BMODE        <- 0x0005

MMODE        <- 0x0005

 

\\LOAD FIRMWARE

STAGE        <- 0x0005

IADDR        <- 0x0000

IDATA        <- 0xe59f

IDATA        <- 0xf018

.

.

.

IDATA        <- 0x0000

 

 

BOOT         <- 0x008d

wait4 20us

BMODE        <- 0x0025

MMODE        <- 0x0009

 

\\ENCODE PARAMETERS

STAGE        <- 0x0005

IADDR        <- 0x7f00

IDATA        <- 0x0400

IDATA        <- 0x0103

IDATA        <- 0x0201  

IDATA        <- 0x0000

IDATA        <- 0x0000  

IDATA        <- 0x0000  

IDATA        <- 0x004f

IDATA        <- 0x0001  

 

\\INDIRECT REGISTERS

MMODE        <- 0x0005

STAGE        <- 0xffff

IADDR        <- 0x0400

IDATA        <- 0x0004

 

STAGE        <- 0xffff

IADDR        <- 0x040c

IDATA        <- 0x0040

STAGE        <- 0xffff

IADDR        <- 0x0410

IDATA        <- 0x0040

STAGE        <- 0xffff

IADDR        <- 0x041c

IDATA        <- 0x0001

STAGE        <- 0xffff

IADDR        <- 0x0424

IDATA        <- 0x0040

STAGE        <- 0xffff

IADDR        <- 0x042c

IDATA        <- 0x0001

STAGE        <- 0xffff

IADDR        <- 0x0430

IDATA        <- 0x0040

STAGE        <- 0xffff

IADDR        <- 0x0448

IDATA        <- 0x003F

STAGE        <- 0xffff

IADDR        <- 0x044C

IDATA        <- 0x00A6

 

STAGE        <- 0xffff

IADDR        <- 0x141c

IDATA        <- 0x0002    FFTHRC

 

 

EIRQIE       <- 0x0400  

wait for IRQ (low)

EIRQFLG[10]  -> 1

SWFLAG       -> 0xff82 (OK)

 

EIRQFLG      <- 0xffff

 

VSTRB        <- '1'

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