board definition files query
Take a look at PicoZed SDR (AD9361/ZC7035) project(s) locations? .
Are you trying to ask "Vivado board definition files for ADRV9361x designs"?
The answer is that we don't provide a "3rd party download and install" files as an add-on to vivado.
However this is just a cosmetic part. These xml files are nothing more than the tcl files we provide.
As an example, to build your own system.
In IPI, source the adrv9361z7035_bd.tcl to create the SOM block design.
(You will need some helper tcl files those are in the scripts folder).
In Vivado Implementation, source the xdc file for the SOM part.
You can customize, add and other things to this as you wish. The tricky part is - you must source our board design first (as it newly creates the interconnects and address maps) and then add your customization on top of it. If not, you will have to override some of the variables (if this is what you want to do, let us know we will help you).
If you are really picky, you can just use the PS7 preset parts of the adrv9361z7035_bd.tcl and leave the rest out.
i tried building system files but while running https://github.com/analogdevicesinc/hdl/blob/dev/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl this file, i am getting error which says
invalid command name "ad_ip_instance
"ad_ip_instance processing_system7 sys_ps7"
(file "adrv9361z7035_bd.tcl" line 57)
hi, the above issue got resolved after running tcl files from the script folder.but now there is error while running one tcl file form script folder
error :[common 17-170] Unknown option '-detail',please type 'report_timing -help' for usage info.
Hi,Look at Building HDL [Analog Devices Wiki] .The easiest way is to use make Andrei
thanks , i could build project using make.but the link which u sent https://github.com/analogdevicesinc/hdl/blob/dev/projects/adrv9361z7035/common...
in this folder there is no make file
kindly send me the link for the make file which i need to use for Picozed SDR
Did you clone the hdl github repository as explained in Building HDL [Analog Devices Wiki] ?Don't use dev branch, that goes undercharges daily and things will eventually brake, use hdl_2017_r1 branch (the 2017_r1 is a prerelease and is under testing process, it is not excluded that you might encounter some bugs)
hdl_2017_r1 (hdl/projects/adrv9361z7035 at hdl_2017_r1 · analogdevicesinc/hdl · GitHub )
There you have to chose your carrier (ex. ccbob_lvds )You will find a Makefile in each folder.
can u tell me the link for the latest software for ad9361?
Hi,no-OS/ad9361 at master · analogdevicesinc/no-OS · GitHub Andrei
can u please send me sdk project for ad9361..
Hi,We prefer not to send build projects. Helping you understanding the flow and building it is the goal.Take a look at: AD9361 No-OS Software [Analog Devices Wiki] make sure you uncomment no-OS/config.h at master · analogdevicesinc/no-OS · GitHub and no-OS/config.h at master · analogdevicesinc/no-OS · GitHub.Andrei
,Actually i am getting some errors while building sdk project.
fatal error:platform.h:no such file or directory
and when i add this .h file,
then error is: multiple markers at this line
can u give me any link for building sdk project?
Hi,I presumed that AD9361 No-OS Software [Analog Devices Wiki] , had all the explanations required to build a project, I see that it must be updated.
Add all files in platform_xilinx no-OS/ad9361/sw/platform_xilinx at master · analogdevicesinc/no-OS · GitHub to your project. As described in github README section.
I will add a make flow to the 2017_R1 release to avoid all this.There are some scripts there to build the project now:you have to copy the system_top.hdf in the no-OS (github/no-OS/ad9361)
-create_xilinx_sdk_project.bat for windows-make for linux
i am trying to follow these steps for building sdk project AD9361 No-OS Software [Analog Devices Wiki] .but there i am having problems like do all files like ad9361/sw and ad9361/sw/platform_xilinx to be added in src folder as only ad9361/sw /platform_xilinx files are getting added there .for ad9361/sw files. there comes a warning that it is not a valid hardware specification file.
then i tried to follow xsct terminal path. there also getting some errors
also tried vivado tcl shell..and tried to build project using makefile.zynq..there also some error
which is the easiet method for building sdk project?
As i am new to this field kindly help me
Hi Apurva,The first thing to solve is that warning with not a valid hardware specification file (system_top.hdf).Let's build this project manually Did your hdl build run trough fine?Start SDK and create a new hardware platform resources:fpga:xilinx:create_new_hardware.png [Analog Devices Wiki] point it to the resulted system_top.hdf from the hdl build.
Then create the empty application project and then build it.
Let me know if you still see any issues with the hardware platform.All sources from ad9361/sw and ad9361/sw/platform_xilinx go into src.Andrei
yes my hdl was built..them i export hardware in vivado and then launched SDK
then i created new application project and tried adding these files to src folder
in sdk_log..these warnings are shown
Hi,You misunderstoodAll *.c and *.h files in ad9361 go in sw_ad9361_13_10/src not in system_top_hardware_platform_0.That is your problem Andrei
i could build sdk project now..and .elf file is made..when i am doing Run Configuration ..this error is shown
error while running ps7_init method
can not read from target
Hi,Can you put a printscreen of your Run configuration?Other things to check:-Are you connected to the usb programmer (jtag)?-did you program the bitstream before running the software?Andrei
Printscreen of run configuration
i programmed FPGA before running run configuration..jtag cable is also connected
Hi,It is the first time I see this "MMU section translation fault" error.From the print screen I notice that you have multiple projects inside your SDK workspace, can you clean it up and leave only hw, bsp_sw and sw. Clean, build and program. If it still does't work start on a clean workspace and add just this tree projects.Andrei
it worked..ad9361 got initialized successfully and could see output waveform on spectrum analyser..but it run by doing launch on hardware(system debugger)
thankyou for your support
now my next target is to add my own IP in this reference design like a simple DDS..could u guide me?
Hi,Sorry for the late reply, take a look at this example Adding FIR filters in a fmcomms2 design [Analog Devices Wiki] Andrei
Thanks for your reply
I am trying to run the above example
When I am adding util_fir_int ip ..I am getting this error..
am i missing something?
You have to build the "util_fir_int" library manually or add it into the make dependencies
hdl/Makefile at dev · analogdevicesinc/hdl · GitHub There is a fmcomms2_fir_filters branch that has this example implemented hdl/projects/fmcomms2_fir_filters/zc706 at fmcomms2_fir_filters · analogdevicesinc/hdl · GitHub Andrei
i am trying to run the above example for my picozed sdr kit.for that i build the project by adding libraries manually in the make file and did all the connections. now trying to do synthesis.
got these errors while doing synthesis
then i build the already implemented design for fmcomm2 and did synthesis..got same error
also i see in the block design of fmcomm2...that in ip dac_upack there is a port dma_xfer_in
but it is not there for adrv9361z7035
and in the manual it is given that it needs to be connected for valid and enable signals
HiSomething was not build/exported correct for the axi_ad9361 IP.Can you take a look at it, go in library and see the log files for axi_ad9361 IP, clean and build it manually if necessary. Try to manually add a axi_ad9361_ip in the block design and watch for warnings and such.If you don't find the problem let me know.Andrei
i saw the axi_ad9361_ip.log..it says..these files appear to be outside of the project area...
i deleted the ip ad9361 from the project .and manually added the ip and did all the connections..but still i am getting the same error while doing synthesis..
Also i am doing one more exercise...have doubt related to that too..should i start a new thread for that?
Hi Apurva,I was thinking to check for warnings in the tcl console when you add an extra ip in the design, without building anything, for building.For the axi_ad9361 ip do a "make clean" and "make all" in library/axi_ad9361.
Can you attache the project log and axi_ad9361_ip.log file after you clean it?What is that on what you have doubts?Andrei
i am trying to send a random data to ad9361 ic..for that i generated an ip from system generator, data rate 10MHz converted its output to 16 bits...gave its output to axi_ad9361 core..
Now i am having problem with the clock..this data_generator ip needs 10 mhz clock...i connected it to l_clk..
i dont know the clock output of l_clk..how is it generated?
how the clock is driven?how can i change it according to my need?
l_clk is the system clock you can't just change it.Is generated by the ad9361 () Adding FIR filters in a fmcomms2 design [Analog Devices Wiki] you can take this as a reference.You have a few options to obtain your desired clock:- devide some clock to obtain your desired clock- add and configure a new clock from the the zynq processor- play with the clock wizard ipAndrei
I generated random data of 100 MHz from system generator ..took clock from div clock ip.
And saw the spectrum..it is showing bandwidth of 100 MHz...is it correct? As I did not change the rf_tx_bandwidth..it is 18 MHz..
Hi,What is your goal whit that system generator?The data must be modulated before transmission.Take a look at some MATLAB examples ADI AD9361 System on Module (SOM) SDR [Analog Devices Wiki].Andrei
Iam trying to run simulation for the reference design...hdl-hdl_2017_r1...getting errors...
Do I need some other files for it?
Hi,We don't support testbenches/simulations for the reference design. You can add your own starting from IP level or you can add ILAs trough the design and start understanding it like that.For start you can find examples of ILAs in: Adding FIR filters in a fmcomms2 design [Analog Devices Wiki]
More info Integrated Logic Analyzer (ILA) Andrei
its been long and m stuck in the same problem...actually my goal is to do BPSK Modulation in HDL and give this to AD9361....for that i generated a random data say 15 bit PN data...converted it to 16 bit..most positive value is0x7ff and most negative to 0x800....for that i divided the l_clk by 2(l_clk is 61.44 MHz in my design)...i gave this output to FIFO generator ...in FIFO...RD_enable is given a constant 1 and wr_enable is connected to dac_valid of axi_AD9361 core..fifo clock is connected to l_clk too...fifo output is conneccted to data_i and data_q of axi_ad9361(which is now BPSK IQ data)....
but m not seeing any changed in the spectrum..still seeing the same peak which is coming in the reference design..what else should i change in my design?am i on the right track??
If you are seeing a sinewave on the output, this is coming from the DDS modules, you can chose your data source by writing in reg 0x4418 (REG_CHAN_CNTRL_7) to select the DMA input. See block diagram: AXI_AD9361 [Analog Devices Wiki] and the register map AXI_AD9361 [Analog Devices Wiki] .hdl/axi_ad9361_tx_channel.v at hdl_2017_r1 · analogdevicesinc/hdl · GitHub
You have 4 channels make sure you correctly set your data source in software for each one
- hdl/axi_ad9361_tx.v at hdl_2017_r1 · analogdevicesinc/hdl · GitHub
- hdl/axi_ad9361_tx_channel.v at hdl_2017_r1 · analogdevicesinc/hdl · GitHub
- hdl/up_dac_channel.v at hdl_2017_r1 · analogdevicesinc/hdl · GitHub
Regarding your FIFO generator, I don't have a clear picture on data paths, rates and such. You can look for example/descriptions at that fmcomms2 filters previously mentioned, if things are still unclear, make a diagram of path you are struggling with, post it and lets start from there.
About the "right path", one can add data processing modules and interface it the ad9361 directly or trough a FIFO(easier to handle different clock domains and data width paths).
Thankyou Andrei...now the data is sent after setting the register..this is how the spectrum looks like:
data rate =30.42 MSPS...BPSK modulated signal
Also now if i want to change the data rate of the input??what should i do?should i change the sampling frequencies of the filter chain??
this is what i have done in the block design..i gave my IQ data to axi_ad9361_dac_fifo and generated a valid signal and gave it to din_valid_in_0 and din_valid_in_1..Am i on the right track??
Hi Apurva,To change the data rate can simply call: ad9361_set_rx_sampling_freq()
ad9361_set_tx_sampling_freq()no-OS/ad9361_api.c at master · analogdevicesinc/no-OS · GitHub Only in case you want your sampling rate to be lower than 2MSPS you have to modify the filter chain.
Take a look at this UTIL_RFIFO [Analog Devices Wiki].Andrei
i want to design a modem which is variable data rate?
what should i do for that?
like i want a control signal as an input to my HDL design which can configure my modem
Hi Apurva,Please start another thread for the last question, we already deviated a lot from the original purpose of this thread.
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