I am using the axi_i2s_adi (hdl_2017_r1 branch) IP block in a Zynq Ultrascale+ (ZCU102 ES1 Board) Vivado 2017 design and finding tlast is always asserted. From the VHDL code I can see there is a PERIOD_LEN_REG register and modifying the values to 0x0004 0x0010 did not resolve this issue.
BCLK_DIV_RATE = 3
LRCLK_DIV_RATE = 24
The AXI I2S is configured as shown below.
PERIOD_LEN_REG = 0