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Problem debugging ADV7511 reference design with Segger J-Link

Question asked by umair_khan on Aug 11, 2017
Latest reply on Aug 30, 2017 by rejeesh

adv7511 hdl reference design

Hello everyone,

 

I am using your ADV7511 HDL reference design on ZC702 evaluation kit. I can't use the onboard debugger that's why I am using J-Link for downloading software on PS. For programming PL with your reference bit stream, I am using a bootable SD card created using FSBL template in Xilinx SDK.
The problem is that if I try to connect J-Link with PS after FSBL completes programming of PL (DONE LED goes green), it can't reset target with following error:


Reset delay: 0 ms
Reset type NORMAL: Toggle reset pin and halt CPU core.
Info: Cortex-A/R (reset): Re-initializing debug logic.

****** Error: Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Command : 10) @ Off 0xB.
Cortex-A/R (connect): Core internal signal DBGEN is not asserted. Debugging is not possible.

 

If I do it without programming the PL, J-Link successfully connects and download/run the software on the PS. I want to ask that is there a way to debug your reference software on PS with JLink. Remember I am connecting J-Link cable at J58. I earlier contacted Xilinx and they replied that its Analog electronics design so they can better help.

 

Thanks,

Umair

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