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AD5452 control hardcode problem(verilog)

Question asked by ASB on Aug 11, 2017
Latest reply on Aug 13, 2017 by isantos

I can't control the DAC correctly. Could you help me?

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module DAC (clk1, sw, sclk, sync, sdin); input clk1; input  sw; output reg [0:0] sclk; output reg [0:0] sync; output reg [0:0] sdin; reg [15:0] sdin_reg; reg [7:0] seq; reg [7:0] cnt1; reg [7:0] cnt2; always @ (negedge clk1 or negedge sw) begin if (!sw) begin

   sclk <= 1;

              sync <= 1;

              sdin <= 1;

              sdin_reg [15:0] <= 16'b0010000000000000;

              seq <= 0;

              cnt1 <= 15;

              cnt2 <= 15;

end

else begin

   case (seq)

                 0:begin

                                sync = 0;

                                sdin_reg [15:0] = 16'b0010000000000000;

                                           cnt1 <= 15;

                                           seq = seq + 1;

                            end

                             1:begin

                                sdin = (sdin_reg [15:0] >> cnt1) & 1;

                                           cnt1 = cnt1 - 1;

                                           seq = seq + 1;

                             end

                             2:begin

                                sclk = 0;

                                           seq = seq + 1;

                             end

                             3:begin

                                sclk = 1;

                                           if (cnt1 == 0) begin

                                              

             seq = seq + 1;

         end

         else begin

                                              

             seq = 1;

         end

                             end

                             4:begin

                                 sync = 1;

          seq = 0;

                             end

                            

 

              endcase

end

end

endmodule

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