I am using a BF537 with SCLK set to 95 MHz connected to a MT48LC16M16A2P-6A SDRAM.
I'm trying to debug some strange results in my project and I'm looking at the EBIU settings.
I've used the calculator reference in BfSdcDmcCalculation_Release.xlsx to determine my `EBIU_SDGCTL` settings based on the attached datasheet for the MT48LC16M16A2P-6A (found here: Micron Technology, Inc. - MT48LC16M16A2P-6A)
My existing code (which I'm trying to debug) sets:
- TRCD to 3
- TRP to 3
- TRAS to 6
Based on the above referenced calculator and the documentation in "ADSP-BF537 Blackfin Processor Hardware Reference", I believe I could set:
- TRCD to 2
- TRP to 2
- TRAS to 4
My understanding is:
- my existing settings merely take longer to complete some SDRAM operations than if I used the smaller, calculated values
- this is not an issue to the SDRAM/SDC interaction as long as I'm not concerned about the slight reduction in SDRAM speed performance
Can anyone tell me if my understanding is correct?
Thanks in advance.