I am using the axi_i2s_adi (hdl_2017_r1 branch) IP block in a Zynq Ultrascale+ (ZCU102 ES1 Board) Vivado 2017 design and finding there is no back-pressure on the DMA when sending a block of 16 u32 words.
BCLK_DIV_RATE = 3
LRCLK_DIV_RATE = 24
The AXI I2S is configured as shown below.
The waveform shows 16 u32 words sent to the AXI I2S and tready goes low and then high before the I2S FIFO has sent the I2S data.
Same waveform as above just zoomed out to show I2S activity.