AnsweredAssumed Answered

AD9684 Byte Mode Problem

Question asked by Vasisuary on Aug 10, 2017
Latest reply on Oct 2, 2017 by J.Harris

Greetings!

 

We are currently trying to configure and debug AD9684 in byte mode. For now we are using 2 DDC (DDC0 and DDC1) which are configured as follows:

Register address     data

x300                       x00

x310                       x40 

x311                       x00  (I and Q inputs from CH A)

x314                       x00

x315                       x04

x330                       x40

x331                       x05  (I and Q inputs from CH B)

x334                       x00

x335                       x04

We are using LVDS byte mode with two converters (reg x568 x15).

But when we apply RF power to CH A input we are seeing zeros (x0000) in I0 and I1 positions (according to Figure 9 of datasheet) and identical sine pattern both in Q0 and Q1.

When we apply RF power to CH B input we are still seeing zeros in I0 and I1 and some noise floor both in Q0 and Q1.

We've managed not to see zeros in I0 and I1 only when changed mixer from real to complex for both DDC0 and DDC1, but still it will only react on power on CH A input, but not on CH B input. And all four I0, Q0, I1 and Q1 looks the same, none of them are quadrature to other.

Also we used user patterns to try to understand what's happening and when we wrote x05 in register x327 (both I and Q test outputs of DDC0 are enabled) we saw our test patterns in all four I0, Q0, I1 and Q1 positions in output frame. When using DD1 test outputs there is nothing on the output.

 

When cofiguring input from CH B for DD0 and input from CH A for DDC1 we are seeing the same picture but now for CH B and CH A (or DDC1) is ignored.

 

I'm including file with register map we are currently using. Could you please look into it and explain us what we have to do to see converted data from bath CH A and CH B inputs simultaneously.

 

Last question: could it be a typo in register address of last register in Table 29 of datasheet (output parallel driver adjust 2)? Could it be not x05B, but x56B? And if yes, could the fact we are now writing x00 in wrong register x05B cause troubles?

 

Best regards,

Igor.

Attachments

Outcomes