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Setting up the ad9739a_fmc_ebz

Question asked by edoutthere on Aug 9, 2017
Latest reply on Aug 21, 2017 by edoutthere

NOTE: I moved this question from high-speed DACs to this section at the suggestion of Chris


I need some general questions answered about the AD9739A and its eval board, the AD9739a-FMC-EBZ. 


I have one of these attached to a zedboard.  I built the HDL and software for the ZC706, learned what it is doing then ported it some of it to the zedboard.  For the HDL part, I am only using the ad9739a_if.v and below, I am feeding its 256-bit bus with my own module.  This placed fine and is running on the ZED FPGA fabric. I implemented the SPI control path on my own, and I am able to read and write the SPI registers on the EBZ.  The clock chip lights it lock LED after being programmed.  I can read and write the DACs SPI registers.  The default register values come back from the DAC
and match the values in the DS (rev D).

As for software, I am using the modules needed to program the clock and DAC chips through the SPI interface.  The eval project was self-explanitory and easy to use.



Using the default settings in the eval, which match the DAC data sheet, I am not getting Mu lock



1.  I am having trouble understanding the procedure for setting slope and delay based on the dac_clk.  Looking at fig 166 in the data sheet, it looks like MU_DELAY of 216 is near the negative slope of 6 "desired phase" point.  The Mu controller will search for this point on its own.  I dont understand how changing the clock input rate will change this decision logic.  Is ADI implying that the wave in fig 166 will spread out as the freq goes down?  Doesn't the Mu delay value LSB value change as the clock freq does, the Mu logic is clocked by the same clock it is measuring.  I think I am missing a key point.

2.  In this forum post:, evandavis sez he is setting the dac_clk to 1Gsps.  The data sheet specifies the DAC_CLK input as having a range of 1.6 to 2.5 GHz.  How does this work, I am asking because:

3.  I too want to use this DAC as a baseband DAC, clock it in the range of 200MHz.  This question: asks just this.  if I set the input clock to 200MHz, will the DAC be able to handle this.  I dont undertand how you can use a DAC_CLK of 2.5GHz with an FPGA.  This means a 625MHz DCO!
Can you suggest DAC register settings to handle this?

4.  the person that responded to analog-archivist said "This will work to some degree. The throughput and full capability of the AD9739A is somewhat quite limited when using with ZED Board".  Can I get a better explanation than "some degree" and "quite limited".
The zedboard has all the correct connections to attach to the EBZ.  I dont kno who responded to the question or I could ask them...

5.  What does the DCO look like if the Mu controller does not lock?  I can change the clock chip output but I always get the same DCO from the 9739.  It varies so much it looks like a data line!

6.  Is the A3 (3.3v) VR supposed to get hot?