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HFCLK for SPDIF Transmitter for ADSP-SC584

Question asked by MZC on Aug 9, 2017
Latest reply on Feb 1, 2018 by Jithul_Janardhanan

Hello,

I have written SPDIF_TalkThrough code on evaluation board ADSP-SC584 where SPDIF Reciever get audio at 96 KHz sample rate and through SPORT 0B get audio in memory and process it and then send processed audio through SPORT 0A to SPDIF Transmitter.

 

SPDIF Receiver provides Bit Clock, FS and HFCLK to SPORTS as well as to SPDIF Transmitter. I connect SPDIF0_RX_TDMCLK_O to SPDIF0_TX_HFCLK_I to provide HFCLK for Transmitter. But SPDIF0_RX_TDMCLK_O is not accurate at it misses pluses. On Page 37-4 of processor Hardware manual it is written,

 

The module clock of the S/PDIF transceiver is SCLK0_0. The clock source for the S/PDIF receiver reference clock
is CLKO5 from the CDU. When CLKO5 is configured, it supports sampling frequencies of 24 kHz to 192 kHz.
The clock to this module may be shut off for power savings.
Sample rates of 24 kHz to 96 kHz are supported using a 170 MHz to 180 MHz setting on CLKO5.
Sample rates of 32 kHz to 192 kHz are supported using a 225.0 MHz setting on CLKO5.  

 

even at setting of 225 MHz, it is highly in accurate.

 

Can u provide the solution how can I use  SPDIF0_RX_TDMCLK_O clock for SPDIF0_TX_HFCLK_I at 96 KHZ?

 

Best Regards,

 

Mussab Zubair

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