I 'm using FMCDAQ2 reference design hw R2017_R1 with no-OS (dev branch) on KC705 carrier.
The RX path (adc testmodes until data captured) seems to be correct, (automatic check of PN sequences, and I recognise the samples on the captured data.
When when I Loop back one DAC to one ADC (1 channel), I could'nt get out on the captured data, the pattern I put in the lut table defined in the dac_buffer.c. (sine_lut_1 and sine_lut_2). This Lut has a size of 2 x 1024 samples, the DAC fifo has size of 8192 samples, please can you tell me what could be the problem ? The pattern I used for example 1 tone of 50 Mhz
sine_lut_1 odd samples , sine_lut_2 even samples (total samples 2048).