I am using the axi_i2s_adi (hdl_2017_r1 branch) IP block in a Zynq+ (ZCU102 ES1 Board) Vivado 2017 design and it is failing timing. See below. Can you help?
The schematic below shows one of the six paths that are failing timing.
Constraint for the AXI I2S IP block.
IP Block configuration