I was curious about recommended clocking methods for the AD9625. Looking at the eval board, there seem to be three options:
- AD9525 PLL/VCO
- Avago wideband VCO
- Qorvo narrowband VCO
I am asking if there is any way to calculate the SNR degradation due to sampling jitter when using one of the open-loop VCOs. For closed-loop PLLs it's relatively straightforward to define a phase noise BW and integrate over that, but the phase noise profile of an open-loop VCO is dramatically different. Any recommendations?