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Direct DAC write

Question asked by PiotrK on Aug 8, 2017
Latest reply on Aug 20, 2017 by NeoXu

Hello,

 

I would like to use DAC to generate trigger signal for external sensor. The trigger signal is a constant voltage in the range 0.5v and 1.8V between AFE3 and ground. I have problem with DAC configuration in the sequencer.

I think, there may be something wrong with switch configuration and instrumentation amplifier but I can't figure it out.

After I run the sequence, voltage on the AFE3 rises to saturation voltage like on the image below (blue line). It should stay at middlescale - 1.1V (sequence[20]). The yellow signal is effect of execution of custom interrupt at sequence[12] (riding edge) sequence[27] (falling edge). 

 

Many thanks for any suggestions.

Piotr

 

 

uint32_t sequence[] = {

0x00210013, /* 0 - Safety Word, Command Count = 18, (CRC software calculations) */
0x84007818, /* 1 - AFE_FIFO_CFG: DATA_FIFO_SOURCE_SEL = 0b11 (LPF) */
0xA0000209, /* 2 - AFE_ADC_CFG: MUX_SEL = 0b01000 (AN_B), GAIN_OFFS_SEL = 0b10 (AUX) */
0xA2000000, /* 3 - AFE_SUPPLY_LPF_CFG: BYPASS_SUPPLY_LPF = 0 */
0x00000640, /* 4 - Wait: 100us */
0x86000000, /* 5 - AFE_SW_CFG: All switches open */

0x84007018, /* 6 - AFE_FIFO_CFG: DATA_FIFO_EN = 0; disable data fifo during settling */
0x800303F0, /* 7 - AFE_CFG: ADC_CONV_EN = 1, SUPPLY_LPF_EN = 1 */
0x00090880, /* 8 - Wait: 37ms for LPF settling */
0x84007818, /* 9 - AFE_FIFO_CFG: DATA_FIFO_EN = 1; enable data fifo */
0x00045880, /* 10 - Wait: 17800us (time necessary to acquire 16 samples) */
0x84007018, /* 11 - AFE_FIFO_CFG: DATA_FIFO_EN = 0; disable data fifo channel */
//16 samples acquired of first channel; toggle channel
0xD2000008, /* 12 - AFE_ANALOG_GEN_INT: CUSTOM_INT = 1. Trigger interrupt. */
0x00090880, /* 13 - Wait: 37ms for LPF settling */
0x84007818, /* 14 - AFE_FIFO_CFG: DATA_FIFO_EN = 1; enable data fifo */
0x00045880, /* 15 - Wait: 17800us (time necessary to acquire 16 samples) */
0x800302F0, /* 16 - AFE_CFG: ADC_CONV_EN = 0 */

 

 

//Generate Trigger signal

0x86000FF3, /* 17 - AFE_SW_CFG: DMUX_STATE = 3 PMUX_STATE = all open NMUX_STATE = all open TMUX_STATE = all open; Connect AFE3 */

0x8A000030, /* 18 - AFE_WG_CFG: TYPE_SEL: 00 Direct write to Dac */
0x88000F00, /* 19 - AFE_DAC_CFG: DAC_ATTEN_EN = 0 */
0xAA000800, /* 20 - AFE_WG_DAC_CODE: DAC_CODE = 0x800, */
0x84007018, /* 21 - AFE_FIFO_CFG: DATA_FIFO_EN = 0; disable data fifo channel */
0x800343F0, /* 22 - AFE_CFG: WAVEGEN_EN = 1, ADC_CONV_EN = 1 */
0x003D0900, /* 23 - Wait: 250ms */
0x84007818, /* 24 - AFE_FIFO_CFG: DATA_FIFO_EN = 1; enable data fifo */
0x00045880, /* 25 - Wait: 17800us (time necessary to acquire 16 samples) */
0x84007018, /* 26 - AFE_FIFO_CFG: DATA_FIFO_EN = 0; disable data fifo channel */
//16 samples acquired of first channel; toggle channel
0xD2000008, /* 27 - AFE_ANALOG_GEN_INT: CUSTOM_INT = 1. Trigger interrupt. */
0x00090880, /* 28 - Wait: 37ms for LPF settling */
0x84007818, /* 29 - AFE_FIFO_CFG: DATA_FIFO_EN = 1; enable data fifo */
0x00045880, /* 30 - Wait: 17800us (time necessary to acquire 16 samples) */
0x84007018, /* 31 - AFE_FIFO_CFG: DATA_FIFO_EN = 0; disable data fifo channel */
0x800302F0, /* 32 - AFE_CFG: WAVEGEN_EN = 0, ADC_CONV_EN = 0; */
0x82000002, /* 33 - AFE_SEQ_CFG: SEQ_EN = 0 */
};

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